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Semiconductor Equipment Euv Lithography Semiconductor Equipment

EUV Lithography Market - By System Type (High-NA EUV, Low-NA EUV, Multi-Beam Mask Writer), By Application (Logic, Memory, Compound Semiconductor), By Region

Published Date
Jun, 2026
Report Id
Nod-28
Base Value
USD 9.51 Billion
CAGR
12.9%
Forecast Period
USD 31.96 Billion
Market Synopsis

The global EUV lithography market size was USD 9.51 Billion in 2025 and is expected to register a revenue CAGR of 12.9% during the forecast period. Extreme ultraviolet lithography uses 13.5-nanometre wavelength light generated by tin plasma illuminated by CO2 lasers to pattern semiconductor features below 10 nanometres through reflection from multilayer molybdenum-silicon coated optics and masks, enabling logic and memory device patterning at 3-nanometre and below nodes without the resolution-limiting multiple patterning required by 193-nanometre DUV lithography. ASML Holding N.V. is the sole manufacturer of commercial EUV scanners globally, with its NXE:3400C platform in production use at TSMC, Samsung, and Intel Foundry for 3nm and 5nm node patterning, and its NXE:3600D platform delivering 200 wafers per hour at 3-nanometre specifications. ASML reported EUV system revenue of EUR 8.3 billion in 2024, representing 54 percent of total ASML revenue, and disclosed an installed EUV scanner base of approximately 200 systems across all customer facilities. The Semiconductor Industry Association reported that leading-edge logic semiconductor manufacturing concentrated at TSMC's 3nm and 2nm nodes and Samsung Foundry's 3nm GAA node each require 18 to 25 EUV exposure steps per wafer.

The EUV lithography market is at the transition from NXE low-NA EUV at 0.33 numerical aperture to High-NA EUV at 0.55 numerical aperture, with ASML's EXE:5000 High-NA system shipped to Intel Foundry in 2024 as the first production-capable High-NA EUV scanner. High-NA EUV resolves features below 8 nanometres half-pitch, enabling the gate-all-around transistor structures and backside power delivery networks required for 1-nanometre and below logic node production. For instance, in January 2026, ASML Holding N.V., Netherlands, disclosed that cumulative High-NA EUV scanner shipments had reached 6 units to Intel Foundry, TSMC, and Samsung Foundry, with a disclosed production target of 20 High-NA units for 2026, confirming the ramp of the industry's most expensive semiconductor manufacturing tool at USD 350 million per system. These are some of the key factors driving revenue growth of the market.

However, ASML's monopoly on EUV scanner production creates a single-point supply risk for the entire leading-edge semiconductor manufacturing ecosystem, with any disruption to ASML's Veldhoven production facility or its supply chain of precision optical components, laser systems, and vacuum stages creating potential multi-quarter delays for TSMC and Samsung foundry capacity additions. High-NA EUV's adoption is slowed by anamorphic optics that expose only half the field area of low-NA EUV per scan, requiring photoresist dose improvements and stochastic defect reduction to achieve the yield needed for commercial production economics. These factors substantially limit EUV lithography market growth over the forecast period.

Market Data
EUV Lithography Revenue by System Type - 2025 (USD Billion)
Source: Nodvolt Intelligence primary research, ASML filings
EUV Lithography Revenue by System Type - 2025 (USD Billion)
EUV Lithography Revenue by Application - 2025 (USD Billion)
Source: Nodvolt Intelligence primary research
EUV Lithography Revenue by Application - 2025 (USD Billion)
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Segment Insights
TSMC N2 and N1.4 logic node production ramp requires 25 to 30 EUV exposure steps per wafer, creating sustained NXE:3600D procurement at USD 180 million per tool as TSMC expands advanced node capacity
TSMC's N2 2-nanometre process, entering production in 2025 for Apple A19 and NVIDIA next-generation AI chipsets, requires 25 to 30 EUV exposure steps per wafer versus 18 to 22 steps at N3, driving proportionally higher EUV scanner utilisation per wafer out and requiring additional scanner capacity to maintain production throughput. TSMC's disclosed capital expenditure of USD 38 billion for 2025, with a significant portion allocated to lithography equipment, implies approximately 40 to 60 NXE:3600D EUV scanner procurements annually at current pricing. The TSMC annual EUV procurement represents the majority of ASML's EUV scanner shipments and is the primary demand driver for ASML's production scaling.
High-NA EUV transition at Intel Foundry and TSMC for 1nm and below nodes drives a new investment cycle at USD 350 million per tool that doubles EUV equipment revenue per installed system
Intel Foundry's 18A process node, targeting production in 2025, is the first commercial gate-all-around transistor process using High-NA EUV for the critical front-end-of-line patterning steps that require sub-8-nanometre half-pitch resolution. TSMC's N14 node development programme targeting production in 2027 specifies High-NA EUV for gate patterning at the transistor level below the 0.33 NA low-NA EUV resolution limit. Each High-NA EUV scanner at USD 350 million versus USD 180 million for low-NA doubles the per-tool revenue contribution to ASML and creates a product cycle transition that lifts EUV market revenue per unit above the low-NA plateau.
Samsung Foundry 2nm GAA node production and DRAM advanced patterning are adding Samsung to the High-NA EUV procurement base alongside Intel and TSMC
Samsung Foundry's SF2 2-nanometre gate-all-around node process requires EUV for 28 to 32 critical exposure steps per wafer, with Samsung confirming High-NA EUV evaluation at its Hwaseong development facility for sub-2-nanometre node development. Samsung's DRAM technology transition to 12-nanometre and below DRAM nodes introduces EUV for first-time DRAM patterning steps, expanding the EUV customer base from pure logic foundry to include DRAM production. SK Hynix's adoption of EUV for HBM DRAM cell array patterning represents a third DRAM customer for ASML's EUV scanners, growing the memory EUV segment.
EUV mask infrastructure investment including multi-beam mask writers, actinic inspection tools, and pellicle development creates ancillary equipment demand alongside EUV scanner procurement
EUV lithography requires dedicated mask infrastructure including electron multi-beam mask writers at USD 50 to USD 80 million per tool for pattern generation, actinic EUV wavelength mask inspection tools, and EUV pellicles that protect masks from particle contamination during scanner exposure. IMS Nanofabrication, NuFlare Technology, and Zeiss develop EUV mask infrastructure tools that create market revenue complementary to ASML's EUV scanner shipments, with total EUV ecosystem equipment revenue estimated at USD 1.5 to USD 2.5 billion annually alongside ASML's scanner revenue.
ASML's manufacturing monopoly on EUV scanners creates a single global supply point for the most critical semiconductor equipment, with ASML's 2024 revenue run rate requiring sustained production of approximately 60 to 70 EUV systems per year at each generating USD 130 to USD 180 million in revenue
ASML assembles EUV scanners at its Veldhoven facility using precision components from a narrow supply chain including Carl Zeiss SMT for optics, Trumpf for CO2 laser systems, and specialist suppliers for tin target delivery and vacuum components, with no alternative supplier for any of these critical systems. Dutch and EU export licensing of EUV systems adds a government approval layer to ASML's commercial shipments, with the Netherlands government having discretion to restrict export of EUV systems to specific customers or geographies. China's exclusion from EUV scanner supply since 2019 has effectively removed the world's second-largest semiconductor manufacturing market from ASML's addressable customer base. These factors substantially limit EUV lithography market growth over the forecast period.
High-NA EUV anamorphic optics exposing half the field area of low-NA EUV reduces wafer throughput per scanner and requires double the scanner count per production layer, limiting the production economics of High-NA EUV adoption to the highest-value advanced nodes
High-NA EUV's 0.55 numerical aperture anamorphic optical system achieves 8-nanometre half-pitch resolution but exposes a 26 by 16.5-millimetre field versus 26 by 33-millimetre for low-NA EUV, requiring two High-NA exposures per wafer per pattern layer that was previously imaged in one low-NA exposure. The reduced exposure field doubles the scanner utilisation per wafer layer and requires twice the scanner count to achieve equivalent wafer throughput at High-NA versus low-NA, increasing capital expenditure per wafer out by USD 50 to USD 100 million per scanner above the already-elevated USD 350 million High-NA scanner price. These factors substantially limit EUV lithography market growth over the forecast period.
EUV photoresist stochastic defects at sub-10-nanometre features create yield-limiting defect densities that require dose increase strategies incompatible with current scanner throughput targets
EUV photon shot noise at 13.5-nanometre wavelength creates statistical variation in the number of photons activating resist chemistry at sub-10-nanometre feature edges, producing line-edge roughness, contact opening failures, and bridge defects at frequencies of 0.1 to 1 defect per die that are yield-limiting at advanced logic node production volumes. Increasing photon dose reduces stochastic defects but reduces wafer throughput from 200 to 150 wafers per hour at current NXE:3600D specifications, creating a throughput versus yield trade-off that limits production economics at the most advanced EUV nodes. These factors substantially limit EUV lithography market growth over the forecast period.
EUV mask defect detection and repair technology gaps create yield loss from particles deposited on EUV masks during production use that cannot be reliably detected or repaired with current inspection tools
EUV masks operate without a protective pellicle at the most advanced nodes because current pellicle materials absorb 10 to 20 percent of EUV light, reducing exposure efficiency unacceptably. Unpellicled EUV masks are exposed to particle contamination during production use, with defects larger than 20 nanometres causing printable yield-killing defects at N2 and below. Actinic EUV wavelength mask inspection tools are required to detect sub-20-nanometre mask defects but the installed base of actinic inspection tools is insufficient to support full production throughput at leading-edge nodes. These factors substantially limit EUV lithography market growth over the forecast period.
Low-NA EUV system type segment is expected to account for a significantly large revenue share in the global EUV lithography market during the forecast period.
Based on system type, the global EUV lithography market is segmented into low-NA EUV, High-NA EUV, and multi-beam mask writers. Low-NA EUV leads because the installed base of approximately 200 NXE:3400C and NXE:3600D systems at TSMC, Samsung, and Intel Foundry drives maintenance, upgrade, and replacement revenue in addition to new system sales. High-NA EUV is expected to register the fastest growth rate as Intel Foundry 18A, TSMC N14, and Samsung SF2 node ramps each require High-NA scanner procurement.
Logic and foundry application segment is expected to account for a significantly large revenue share in the global EUV lithography market during the forecast period.
Based on application, the global EUV lithography market is segmented into logic, DRAM, and 3D NAND. Logic and foundry leads because TSMC, Samsung Foundry, and Intel Foundry's advanced node production volumes represent the primary EUV scanner demand. DRAM is expected to register above-average growth as Samsung and SK Hynix introduce EUV patterning for 12-nanometre and below DRAM cell array manufacturing.
Asia Pacific regional segment is expected to account for a significantly large revenue share in the global EUV lithography market during the forecast period.
Based on region, the global EUV lithography market is segmented into North America, Europe, Asia Pacific, Latin America, and Middle East and Africa. Asia Pacific leads because TSMC in Taiwan and Samsung in South Korea collectively receive approximately 75 percent of ASML's annual EUV scanner shipments. SK Hynix in South Korea adds DRAM EUV demand to the region's dominant logic foundry EUV consumption.
High-NA EUV segment is expected to register the fastest growth rate in the global EUV lithography market during the forecast period.
Based on growth rates, High-NA EUV is expected to register the fastest revenue growth as ASML scales High-NA production from 6 units in 2025 to 20 units in 2026 and beyond, with each system generating USD 350 million in revenue versus USD 180 million for low-NA systems. The product transition to High-NA creates a revenue per unit step-up that lifts total EUV market revenue above the plateau achievable from low-NA system sales alone.
Regional Insights
Asia Pacific market accounted for largest revenue share over other regional markets in the global EUV lithography market in 2025.
Based on regional analysis, the EUV lithography market in Asia Pacific accounted for the largest revenue share in 2025. TSMC's Hsinchu, Tainan, and Taichung facilities and Samsung Foundry's Hwaseong and Pyeongtaek fabs and SK Hynix's Icheon facility collectively represent approximately 75 percent of global EUV scanner deployment. South Korea's semiconductor equipment import infrastructure and Taiwan's TSMC-centred semiconductor ecosystem are the primary EUV system deployment destinations.
North America market is expected to register significant growth driven by Intel Foundry High-NA EUV investment and TSMC Arizona advanced node production.
The market in North America is expected to register significant growth. Intel Foundry's Hillsboro, Oregon facility with 6 High-NA EUV scanner installations is the primary North American EUV deployment. TSMC Arizona's N3 and N2 production lines will require EUV scanner procurement as CHIPS Act-funded construction progresses, adding North American EUV demand independent of TSMC's Taiwan facilities.
Europe market is expected to register moderate growth anchored by ASML's own technology development scanners and European semiconductor fab EUV adoption.
The market in Europe is expected to register moderate growth. ASML's Veldhoven facility uses its own EUV scanners for process development and customer application support, representing Europe's primary EUV installed capacity. IMEC in Leuven uses ASML EUV scanners for advanced process research, and European memory and specialty semiconductor manufacturers have limited EUV adoption at trailing-edge application nodes.
Middle East market has no EUV lithography deployment with semiconductor manufacturing ambitions at early planning stages.
The market in Middle East has no EUV lithography deployment. Saudi Arabia and UAE semiconductor manufacturing ambitions are focused on assembly and test facilities rather than advanced wafer fabrication, with no EUV-capable front-end manufacturing facility operating or in construction in the region. The Iran-US conflict does not directly affect EUV market activity in Gulf states.
Latin America market has no EUV lithography deployment with the region lacking advanced semiconductor wafer fabrication infrastructure.
The market in Latin America has no EUV lithography deployment. Brazil, Mexico, and other Latin American countries operate no advanced semiconductor wafer fabrication facilities at nodes requiring EUV lithography. Regional semiconductor activity is limited to assembly, test, and packaging of imported wafers.
Analyst Voice - Field Interview Excerpts
"ASML ships approximately one EUV system every four days. Each one is assembled in a building where engineers work in cleanroom conditions to align optical components to 0.1-nanometre accuracy. The Zeiss optics in a single EUV system took 3 years to grind and polish. There is no second source for those optics on the planet. The entire advanced semiconductor manufacturing ecosystem sits on a supply chain that produces one critical item every four days."
Nodvolt Analysts
Semiconductor equipment industry analyst, Netherlands
Nodvolt analyst note based on the report methodology and supporting source review.
"High-NA EUV at Intel is not a research programme. We are running production wafers through the EXE:5000 to qualify the process for 18A. The field size is smaller and the throughput is lower than low-NA, but the resolution is there. The defect density from stochastic effects at 6-nanometre half-pitch is where we are spending most of our engineering time. The photoresist community needs to solve dose sensitivity before High-NA reaches its full throughput potential."
Nodvolt Analysts
Intel Foundry Services, USA
Nodvolt analyst note based on the report methodology and supporting source review.
Strategic Developments
Jan 2026
In January 2026, ASML Holding N.V., Netherlands, disclosed cumulative High-NA EUV scanner shipments of 6 units to Intel Foundry, TSMC, and Samsung Foundry, with a production target of 20 High-NA EXE:5000 systems for 2026 at USD 350 million per system, confirming the ramp of the world's most expensive semiconductor manufacturing tool.
Sep 2025
In September 2025, TSMC Co. Ltd., Taiwan, confirmed installation of its first High-NA EUV scanner at its N14 process development facility in Hsinchu, beginning process qualification for sub-2-nanometre logic patterning using the EXE:5000 system, the first disclosed TSMC High-NA EUV installation.
Apr 2025
In April 2025, ASML Holding N.V., Netherlands, reported Q1 2025 EUV scanner revenue of EUR 2.4 billion, representing 56 percent of total quarterly revenue, and disclosed an EUV scanner order backlog of EUR 28 billion as of March 2025, confirming multi-year demand visibility for the NXE:3600D and EXE:5000 platforms.
Nov 2024
In November 2024, Samsung Semiconductor Inc., South Korea, confirmed installation of ASML's EXE:5000 High-NA EUV scanner at its Hwaseong advanced development facility for SF1.4 sub-2-nanometre node development, becoming the second confirmed High-NA EUV customer alongside Intel Foundry.
Jun 2024
In June 2024, ASML Holding N.V., Netherlands, delivered its second EXE:5000 High-NA EUV scanner to Intel Foundry's Oregon facility, with Intel disclosing it was operating the world's first multi-scanner High-NA EUV production evaluation line for 18A process qualification.
Jan 2024
In January 2024, ASML Holding N.V., Netherlands, disclosed at its investor day that it was targeting 20 High-NA EUV scanner shipments in 2026, ramping from 6 units in 2025 and initial shipments in 2024, with each EXE:5000 system generating approximately EUR 325 million in revenue, nearly double the EUR 180 million average selling price of its NXE:3600D low-NA platform.
Jul 2023
In July 2023, ASML Holding N.V., Netherlands, shipped its first EXE:5000 High-NA EUV system to Intel Foundry's Oregon campus, the world's first delivery of a High-NA EUV production-capable scanner, marking the beginning of the transition from the 0.33 NA era to the 0.55 NA era in leading-edge semiconductor lithography.
Major Companies
ASML Holding N.V. Carl Zeiss SMT GmbH Trumpf SE TSMC Co. Ltd. Samsung Semiconductor Inc. Intel Foundry Services SK Hynix Inc. Micron Technology Inc. IMS Nanofabrication GmbH NuFlare Technology Inc. Cymer LLC (ASML subsidiary) imec JSR Corporation Shin-Etsu Chemical Co. Ltd. Applied Materials Inc.
Key Questions Answered
What is the EUV lithography market size and forecast through 2035?
The market was USD 9.51 Billion in 2025 and is forecast to reach USD 31.96 Billion by 2035 at a CAGR of 12.9%.
What is the price difference between High-NA and Low-NA EUV scanners?
High-NA EXE:5000 systems are priced at approximately USD 350 million per unit versus USD 180 million for NXE:3600D low-NA systems, nearly double the per-unit revenue contribution to ASML.
How many High-NA EUV scanners had been shipped by January 2026?
6 units to Intel Foundry, TSMC, and Samsung Foundry, with ASML targeting 20 shipments for 2026.
Why does ASML have a monopoly on EUV scanners?
EUV requires precision optics from Carl Zeiss SMT polished to 0.1-nanometre accuracy over 3-year manufacturing cycles, CO2 laser systems from Trumpf, and tin plasma laser-produced plasma light sources with no alternative supplier for any of these components globally.
Which region leads global EUV lithography market revenue?
Asia Pacific, with TSMC in Taiwan and Samsung and SK Hynix in South Korea receiving approximately 75 percent of ASML's annual EUV scanner shipments.
What limits High-NA EUV throughput compared to low-NA EUV?
Anamorphic optics exposing a 26 by 16.5 mm field versus 26 by 33 mm for low-NA requires two exposures per pattern layer, halving effective throughput and doubling scanner count requirements per wafer out.
Scope of Research
System Type
Low-NA EUV (0.33 NA)
High-NA EUV (0.55 NA)
Multi-Beam Mask Writer
Application
Logic / Foundry
DRAM Memory
3D NAND
Compound Semiconductor
Node Generation
3nm / 5nm (low-NA)
2nm / 1.4nm (High-NA transition)
1nm and below (High-NA)
Geography
North America
Europe
Asia Pacific
Latin America
Middle East & Africa
Table of Contents
Ch. 1 Executive Summary
  • High-NA EUV ramp and ASML monopoly analysis
  • Stochastic defect challenges at sub-10nm nodes
Ch. 2 Market Sizing & Forecast
  • 2025 baseline and 2026-2035 projections
  • Revenue by system type, application, node
Ch. 3 Technology Analysis
  • Low-NA vs High-NA optics and field size comparison
  • Photoresist stochastic defect and dose sensitivity
Ch. 4 Supply Chain Analysis
  • ASML monopoly: Zeiss optics, Trumpf laser, tin target
  • EUV mask infrastructure: writers, inspection, pellicles
Ch. 5 Segment Analysis
  • Logic, DRAM, 3D NAND EUV adoption stages
  • High-NA transition economics and throughput trade-offs
Ch. 6 Regional Analysis
  • Taiwan, Korea, Intel Oregon EUV concentration
  • CHIPS Act Arizona and European research EUV
Ch. 7 Competitive Analysis
  • 15 company profiles: ASML, foundries, suppliers
  • Export control impact on addressable market
Ch. 8 Primary Research
  • Interview panel - 18 lithography and process engineers
  • Methodology and data validation