Custom AI ASIC (XPU) Market - By Design Model (Full Custom In-House, Co-Designed with ASIC Partner), By Workload (Training, Inference, Video and Recommendation), By Program Owner (Google TPU, AWS Trainium/Inferentia, Meta MTIA, Microsoft Maia, OpenAI and Emerging), By Region

The global custom AI ASIC market size was USD 34.62 Billion in 2025 and is expected to register a revenue CAGR of 23.5% during the forecast period. A custom AI ASIC, commonly termed an XPU, is an accelerator designed by or for a single operator against its own workloads, spanning Google's TPU family, Amazon's Trainium and Inferentia, Meta's MTIA, Microsoft's Maia, and emerging programmes including OpenAI's co-designed accelerator with Broadcom. The design model splits between full custom in-house teams and co-design partnerships in which Broadcom and Marvell supply SerDes, packaging, HBM integration, and physical design, with Broadcom disclosing AI semiconductor revenue above USD 20 billion for fiscal 2025 driven substantially by custom accelerator programmes and guiding a serviceable addressable market of USD 60 billion to USD 90 billion by 2027 for its custom silicon customers. Google's seventh generation TPU Ironwood, launched to general availability in November 2025, scales to 9,216 chips per pod and anchors the largest deployed XPU fleet.

Inference economics at hyperscale is the primary revenue growth driver, because operators serving trillions of tokens daily capture cost per token advantages by matching silicon to their own serving stacks, and internal workloads provide guaranteed volume that de-risks each tape-out. Amazon disclosed that its Trainium2 fleet, deployed at scale in Project Rainier for Anthropic across approximately 500,000 chips in 2025, became its fastest-scaling infrastructure programme, with Anthropic and OpenAI emerging as the largest committed Trainium consumers, and Amazon detailed Trainium3 at re:Invent 2025 with volume deployment through 2026. OpenAI and Broadcom announced a multi-year collaboration in October 2025 to deploy 10 gigawatts of custom accelerators from 2026, the largest single custom silicon commitment disclosed to date. For instance, in November 2025, Google LLC, USA, launched its Ironwood TPU to general availability, disclosing pod configurations of up to 9,216 liquid-cooled chips with above 42 exaflops of FP8 compute per pod and positioning the generation for large-scale inference serving alongside training. These are some of the key factors driving revenue growth of the market.

However, custom silicon programmes carry concentrated execution risk that merchant buyers never face, because a delayed tape-out or underperforming generation strands a single operator's roadmap with no alternative supplier, and each programme must rebuild compiler, kernel, and framework support that the merchant ecosystem amortises across thousands of customers. Software maturity remains the persistent gap, as internal accelerators serve narrower workload sets than CUDA-class ecosystems and every model architecture shift risks obsoleting silicon optimised for the previous one. The programmes also compete for the same constrained inputs as merchant GPUs, TSMC leading edge wafers, sold-out HBM, and advanced packaging, without the volume leverage of the largest merchant buyer, and US export controls remove Chinese hyperscalers from the addressable market while pushing them toward domestic ASIC programmes that will eventually compete in third markets. These factors substantially limit custom AI ASIC market growth over the forecast period.