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3D IC and Through-Silicon Via Interconnect Market - By TSV Type (Via-First, Via-Middle, Via-Last), By Application (Memory Stacking, Logic-on-Logic, Sensor Integration, Photonics), By Region
Published Date
Jun, 2026
Report Id
Nod-3
Base Value
USD 6.24 Billion
CAGR
15.4%
Forecast Period
USD 26.18 Billion
Market Synopsis
The global 3D IC and through-silicon via interconnect market size was USD 6.24 Billion in 2025 and is expected to register a revenue CAGR of 15.4% during the forecast period. Through-silicon via technology creates vertical electrical connections through semiconductor die by etching high-aspect-ratio holes at 5 to 10 micrometre diameter and 50 to 100 micrometre depth, depositing insulating liner and barrier layers, and filling with copper or tungsten conductor to enable die-to-die electrical connections in 3D stacked integrated circuits. TSV processes are classified by integration sequence: via-first TSVs etched before front-end transistor processing, via-middle TSVs integrated between front-end and back-end metallisation, and via-last TSVs etched from the wafer backside after all processing is complete. The HBM DRAM market is the highest-volume TSV application, with SK Hynix, Samsung, and Micron using via-middle TSVs to interconnect 4 to 12 DRAM dies per HBM stack at 50,000 to 100,000 TSVs per stack. SEMI reported that TSV-capable semiconductor manufacturing equipment represented USD 2.1 billion in wafer fab equipment spending in 2024, growing 24 percent year-on-year.
The 3D IC TSV interconnect market is being driven by HBM memory's structural coupling to AI accelerator demand, CMOS image sensor backside illumination and stacking technologies using TSVs for pixel die to logic die connection in Sony, Samsung, and OmniVision sensors, and Intel Foveros and TSMC SoIC logic-on-logic 3D stacking approaches that use TSVs or hybrid bonding for high-density die-to-die interconnects. Sony's IMX sensor series for smartphone cameras uses via-last TSVs for front-illuminated to back-illuminated structure with stacked image signal processor die, with Sony selling approximately 1.5 billion image sensor die annually that increasingly incorporate TSV connectivity. For instance, in March 2026, imec, Belgium, demonstrated a 3D IC test structure combining via-middle TSV memory stacking at 3-micrometre via diameter with hybrid bonding at 1-micrometre pad pitch, achieving 10 terabytes per second die-to-die bandwidth in a 4-die stack, the highest 3D IC interconnect bandwidth density demonstrated at the research institute level. These are some of the key factors driving revenue growth of the market.
However, TSV processing adds 3 to 7 additional process steps to semiconductor manufacturing including deep reactive ion etching, atomic layer deposition liner, electrochemical copper plating, and chemical mechanical planarisation, each adding cost and yield risk relative to planar 2D integration. The mechanical stress from TSV copper's thermal expansion coefficient mismatch with silicon creates keep-out zones around each TSV where transistor performance is degraded, reducing active die area by 10 to 15 percent for dense TSV arrays relative to equivalent planar die without TSV integration. These factors substantially limit 3D IC and TSV interconnect market growth over the forecast period.
Market Data
3D IC TSV Market Revenue by Application - 2025 (USD Billion)
Source: Nodvolt Intelligence primary research, SEMI data
3D IC TSV Market Revenue by TSV Type - 2025 (USD Billion)
Source: Nodvolt Intelligence primary research
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Segment Insights
HBM DRAM stacking using via-middle TSVs for AI accelerator memory integration is the dominant TSV demand source, with 50,000 to 100,000 TSVs per HBM stack at 8 to 12 stacked dies
Each HBM3E stack uses via-middle TSVs at 5 to 8 micrometre diameter connecting 8 to 12 DRAM dies at an interconnect density of 10,000 to 20,000 TSVs per square millimetre through the die stack, creating approximately 50,000 to 100,000 TSV interconnects per completed HBM stack. SK Hynix's production of 10 million plus HBM3E stacks annually at approximately 100,000 TSVs per stack represents one trillion individual TSV process cycles annually from a single product at a single manufacturer, illustrating the industrial scale of HBM TSV manufacturing. The growth of HBM demand with AI accelerator production directly scales the via-middle TSV market with AI infrastructure investment.
CMOS image sensor BSI and stacked sensor architectures use via-last TSVs for photodiode array to image signal processor die connections enabling the dual-die designs that achieve the highest sensitivity and processing performance in smartphone cameras
Sony's Exmor RS stacked CMOS image sensor, using via-last TSV to connect a back-illuminated photodiode array die to a stacked image signal processor die, achieves 4 times higher full-well capacity and twice the readout speed of equivalent single-die front-illuminated sensors, enabling the 120 frames per second slow-motion video and multi-frame computational photography in iPhone and Samsung Galaxy flagship cameras. Sony, OmniVision, and Samsung each produce hundreds of millions of TSV-interconnected stacked image sensors annually for smartphone cameras, with the stacked image sensor segment representing the second-largest TSV application after HBM.
Intel Foveros 3D stacking and TSMC SoIC logic-on-logic die integration are establishing TSV-based 3D IC as a production approach for AI processor chiplet integration above 1,000 TOPS compute density
Intel's Meteor Lake client processor uses Foveros 3D stacking with TSV connections at 25-micrometre pitch to attach a thinned compute tile die face-to-face on a base die, enabling processor-memory bandwidth of 100 gigabytes per second through 40,000 TSV interconnects per square centimetre. TSMC's SoIC integration platform combines wafer-on-wafer bonding with TSV connections for logic-on-logic applications, with Apple's M-series Ultra chips using SoIC integration to connect two M-series dies at 4 terabytes per second through a 10,000-TSV interconnect array across the die-to-die interface.
Silicon photonics CPO integration requires TSVs for electrical connection from surface photonics waveguide layers to buried CMOS driver circuits, creating a growing photonics TSV segment as co-packaged optics scales
Silicon photonics modulators and detectors fabricated in the surface layers of a photonics die require TSV connections to the buried CMOS drive electronics at 10 to 50 micrometre pitch, enabling the high-speed electrical-optical interface in CPO platforms from Broadcom, Marvell, and Intel. The CPO market growth at 17.5 percent CAGR creates a derived TSV demand for photonics integration, with each CPO switch ASIC substrate requiring hundreds to thousands of TSV interconnects for photonic device connectivity.
TSV copper-silicon thermal expansion mismatch creates mechanical stress fields extending 5 to 8 TSV diameters from each via, creating keep-out zones that reduce usable transistor area by 10 to 15 percent in dense TSV arrays
Copper's thermal coefficient of expansion at 17 parts per million per Kelvin versus silicon at 2.6 parts per million per Kelvin creates radial stress fields around each TSV that modulate transistor threshold voltage and carrier mobility through piezoresistive effects, degrading transistor performance within 30 to 50 micrometres of each TSV. High-density TSV arrays in HBM and logic stacking applications require keep-out zones that reduce the usable transistor array by 10 to 15 percent relative to equivalent planar die, increasing effective die cost per functional transistor above the cost of silicon substrate alone. These factors substantially limit 3D IC and TSV interconnect market growth over the forecast period.
TSV processing yield loss from deep reactive ion etch non-uniformity, liner deposition, and chemical mechanical planarisation adds 3 to 8 percent total die yield reduction per TSV-processing level relative to planar processes
Each TSV process level adds deep reactive ion etching step coverage non-uniformity, atomic layer deposition liner conformality requirements at 5:1 to 10:1 via aspect ratios, and chemical mechanical planarisation step height control, collectively adding 3 to 8 percent yield loss per TSV-processed die level versus equivalent planar die manufacturing without TSV integration. For HBM 12-die stacks with via-middle TSV on each die, the accumulated yield loss across all 12 dies multiplies the individual die yield penalty, contributing to the 75 to 85 percent HBM stack yield that is significantly below the above-95-percent yield of planar DRAM production. These factors substantially limit 3D IC and TSV interconnect market growth over the forecast period.
Hybrid bonding without TSVs at sub-1-micrometre pad pitch is emerging as a higher-bandwidth alternative to TSV interconnect for logic-on-logic stacking, potentially displacing TSVs in the highest-density interconnect tier
Direct copper-to-copper hybrid bonding at 0.5 to 3-micrometre pad pitch achieves interconnect densities of 100,000 to 4 million connections per square millimetre, compared to TSV interconnect at 100 to 10,000 connections per square millimetre at typical via pitches, with hybrid bonding enabling bandwidth per unit area 10 to 100 times higher than TSV at the die-to-die interface. Intel Foveros Direct, TSMC SoIC-X, and Samsung X-Cube are transitioning from TSV-only to hybrid bonding plus TSV combination architectures for next-generation 3D IC products, with hybrid bonding displacing TSVs for the critical high-density I/O interface while TSVs provide power delivery and signal routing through the die stack. These factors substantially limit 3D IC and TSV interconnect market growth over the forecast period.
Known-good-die testing requirements for each die before TSV assembly add testing cost of USD 5 to USD 20 per die that is not present in monolithic single-die integration, increasing total manufacturing cost of 3D IC products
Testing each die at wafer level before singulation and TSV-based stacking requires full electrical characterisation, thermal stress screening, and in some cases burn-in testing to identify early failure mechanisms before assembly, adding USD 5 to USD 20 per die in testing overhead that scales with die count per stack. For a 12-die HBM stack with 12 individual die test operations plus one completed stack test, the accumulated testing overhead adds USD 60 to USD 240 to the manufacturing cost before any yield loss is accounted for. These factors substantially limit 3D IC and TSV interconnect market growth over the forecast period.
Via-middle TSV type segment is expected to account for a significantly large revenue share in the global 3D IC TSV market during the forecast period.
Based on TSV type, the global 3D IC TSV market is segmented into via-first, via-middle, and via-last. Via-middle leads because HBM DRAM stacking, the largest TSV application, uses via-middle integration, and this type achieves the optimal combination of TSV diameter, depth, and transistor compatibility for memory die stacking. Via-last is expected to register above-average growth as image sensor stacking volume grows with smartphone camera multi-die architectures.
HBM memory stacking application segment is expected to account for a significantly large revenue share in the global 3D IC TSV market during the forecast period.
Based on application, the global 3D IC TSV market is segmented into HBM memory stacking, image sensor stacking, logic-on-logic, photonics integration, and MEMS and sensor. HBM memory stacking leads with approximately 50 percent revenue share. Image sensor stacking is expected to register above-average growth as the stacked CMOS image sensor format extends from smartphones to automotive cameras and industrial machine vision.
Asia Pacific regional segment is expected to account for a significantly large revenue share in the global 3D IC TSV market during the forecast period.
Based on region, the global 3D IC TSV market is segmented into North America, Europe, Asia Pacific, Latin America, and Middle East and Africa. Asia Pacific dominates because SK Hynix, Samsung, and Sony account for the majority of TSV-interconnected semiconductor production in HBM and image sensors, all headquartered and primarily manufactured in South Korea and Japan.
Logic-on-logic application segment is expected to register the fastest growth rate in the global 3D IC TSV market during the forecast period.
Based on growth rates, logic-on-logic 3D stacking using TSV and hybrid bonding combination is expected to register the fastest revenue growth as AI processor chiplet integration at Intel, TSMC, and AMD drives adoption of Foveros and SoIC platforms at production volume, creating new TSV market revenue outside the established HBM and image sensor segments.
Regional Insights
Asia Pacific market accounted for largest revenue share over other regional markets in the global 3D IC TSV market in 2025.
Based on regional analysis, the 3D IC TSV market in Asia Pacific accounted for the largest revenue share in 2025. South Korea's SK Hynix and Samsung produce the majority of HBM DRAM with via-middle TSVs. Japan's Sony produces approximately 1.5 billion stacked image sensor dies annually with via-last TSVs. TSMC in Taiwan provides SoIC logic-on-logic TSV stacking for Apple and NVIDIA customers.
North America market is expected to register significant growth driven by Intel Foveros 3D IC production and CHIPS Act semiconductor manufacturing investment.
The market in North America is expected to register significant growth. Intel Foveros 3D stacking at Chandler, Arizona and Hillsboro, Oregon represents the primary North American TSV-based 3D IC production. CHIPS Act investments in advanced packaging facilities including Arizona State University's JUMP 2.0 centre and commercial OSAT investment are expanding North American TSV processing capability.
Europe market is expected to register moderate growth driven by imec 3D IC research and STMicroelectronics image sensor TSV production.
The market in Europe is expected to register moderate growth. imec in Leuven is the primary European 3D IC research institution, with the March 2026 hybrid bonding plus TSV combination demonstration representing leading-edge European 3D IC research output. STMicroelectronics produces TSV-interconnected image sensors at its Crolles, France facility for automotive camera applications.
Middle East market has no 3D IC TSV production with any future market entry dependent on semiconductor manufacturing infrastructure investment.
The market in Middle East has no 3D IC TSV production. Saudi Arabia and UAE semiconductor manufacturing ambitions focus on less capital-intensive assembly and test operations. The Iran-US conflict does not affect 3D IC TSV market activity in Gulf states.
Latin America market has no 3D IC TSV production with the region serving as a consumer market for TSV-interconnected products manufactured elsewhere.
The market in Latin America has no 3D IC TSV production. TSV-enabled semiconductor products including HBM memory and stacked image sensors are consumed in Latin American electronics markets through imported devices. No advanced wafer fabrication with TSV capability exists in the region.
Analyst Voice - Field Interview Excerpts
"The through-silicon via enabled HBM. HBM enabled Blackwell. Blackwell enabled the large language model era. A 5-micrometre hole in silicon filled with copper is the physical foundation of the entire AI compute infrastructure that exists today. When people talk about AI as a software revolution, they are right, but it is also a materials science achievement that relies on process technologies that took 20 years to mature from research concept to high-volume manufacturing."
Nodvolt Analysts
Leading semiconductor research institution, Belgium
Nodvolt analyst note based on the report methodology and supporting source review.
"We process 50,000 TSVs per HBM die at 5-micrometre diameter through 50 micrometres of silicon. The copper fill is electrochemical. The anneal is thermal. Every TSV has to be void-free or it creates a reliability risk in the field. At 50,000 vias per die and 12 dies per stack, we are qualifying 600,000 individual TSV structures per finished HBM unit. The quality engineering problem at that scale is genuinely difficult and it is what separates the three producers from everyone else."
Nodvolt Analysts
Major DRAM manufacturer, South Korea
Nodvolt analyst note based on the report methodology and supporting source review.
Strategic Developments
Mar 2026
In March 2026, imec, Belgium, demonstrated a 3D IC test structure combining via-middle TSV memory stacking at 3-micrometre via diameter with hybrid bonding at 1-micrometre pad pitch in a 4-die stack achieving 10 terabytes per second die-to-die bandwidth, the highest 3D IC interconnect bandwidth density demonstrated in research.
Oct 2025
In October 2025, SK Hynix Inc., South Korea, disclosed that its HBM4 TSV process used 4-micrometre via diameter versus 5 micrometres in HBM3E, reducing TSV keep-out zone area and increasing active DRAM cell density by 8 percent per die, confirming the link between TSV scaling and DRAM capacity per die in HBM development.
May 2025
In May 2025, TSMC Co. Ltd., Taiwan, announced production availability of its SoIC-X wafer-on-wafer bonding platform combining TSV power delivery with hybrid bonding signal interconnect at 0.9-micrometre pitch, achieving 1 terabyte per second die-to-die bandwidth for logic-on-logic 3D integration in Apple M-series Ultra chip applications.
Jan 2025
In January 2025, Intel Corporation, USA, disclosed Foveros Direct 3.0 integration at 3-micrometre TSV pitch combined with hybrid bonding at 3-micrometre pad pitch for Intel Panther Lake client processor integration, targeting above 1 terabyte per second chip-to-chip bandwidth at a stacking cost below USD 15 per die.
Aug 2024
In August 2024, Samsung Semiconductor Inc., South Korea, announced production readiness of its X-Cube Gen 3 logic-on-logic 3D IC platform with via-middle TSV at 5-micrometre diameter and 40-micrometre depth, targeting AI accelerator compute chiplet plus cache die stacking at bandwidth above 500 gigabytes per second for Samsung Foundry customers.
Feb 2024
In February 2024, Sony Semiconductor Solutions Corporation, Japan, announced the IMX903 stacked CMOS image sensor with 3-layer via-last TSV stacking integrating a dedicated AI processing die below the photodiode array and image signal processor dies, achieving real-time AI scene analysis at 60 frames per second in a single 1-inch optical format sensor for professional video applications.
Sep 2023
In September 2023, Applied Materials Inc., USA, announced commercial availability of its Centura TSV etch and fill cluster tool configured for HBM4 via scaling at 4-micrometre diameter, enabling 20 percent TSV density increase versus HBM3E via dimensions, supporting the via scaling roadmap of SK Hynix, Samsung, and Micron HBM production programmes.
Major Companies
SK Hynix Inc.
Samsung Semiconductor Inc.
TSMC Co. Ltd.
Intel Corporation
Sony Semiconductor Solutions Corporation
imec
Micron Technology Inc.
Applied Materials Inc.
Lam Research Corporation
Tokyo Electron Limited
KLA Corporation
ASE Group
Amkor Technology Inc.
OmniVision Technologies Inc.
GlobalFoundries Inc.
Key Questions Answered
What is the 3D IC TSV interconnect market size and forecast through 2035?
The market was USD 6.24 Billion in 2025 and is forecast to reach USD 26.18 Billion by 2035 at a CAGR of 15.4%.
How many TSVs does a single HBM3E stack contain?
50,000 to 100,000 TSVs at 5 to 8 micrometre diameter, connecting 8 to 12 DRAM dies in a stack with via-middle integration at SK Hynix, Samsung, and Micron.
What bandwidth does the imec 3D IC demonstration achieve?
10 terabytes per second die-to-die bandwidth in a 4-die stack combining 3-micrometre via-middle TSV and 1-micrometre hybrid bonding, demonstrated March 2026.
Why does TSV integration reduce usable transistor area?
Copper-silicon thermal expansion mismatch creates stress fields extending 30 to 50 micrometres from each TSV, degrading transistor performance and requiring keep-out zones that reduce active die area by 10 to 15 percent in dense TSV arrays.
Which region leads global 3D IC TSV market revenue?
Asia Pacific, with SK Hynix and Samsung in South Korea producing HBM with via-middle TSVs and Sony in Japan producing approximately 1.5 billion stacked image sensor dies annually with via-last TSVs.
How is hybrid bonding displacing TSVs in 3D IC applications?
Hybrid bonding at 0.5 to 3-micrometre pad pitch achieves 10 to 100 times higher interconnect density than TSV at comparable pitches, displacing TSVs for high-bandwidth I/O interfaces in Intel Foveros Direct, TSMC SoIC-X, and Samsung X-Cube platforms while TSVs remain for power delivery and long-range routing.
Scope of Research
Tsv Type
Via-First
Via-Middle
Via-Last
Application
HBM Memory Stacking
Image Sensor Stacking
Logic-on-Logic
Photonics Integration
MEMS & Sensor
Via Diameter
1-3 micrometre (advanced)
3-5 micrometre (HBM)
5-10 micrometre (standard)
Geography
North America
Europe
Asia Pacific
Latin America
Middle East & Africa
Table of Contents
Ch. 1
Executive Summary
- HBM TSV dominance and logic-on-logic growth
- Hybrid bonding vs TSV for next-generation 3D IC
Ch. 2
Market Sizing & Forecast
- 2025 baseline and 2026-2035 projections
- Revenue by TSV type, application, via diameter
Ch. 3
Technology Analysis
- Via-first, via-middle, via-last process comparison
- TSV stress and keep-out zone design rules
Ch. 4
HBM TSV Analysis
- HBM3E and HBM4 TSV scaling roadmap
- TSV yield and quality engineering at volume
Ch. 5
Segment Analysis
- HBM, image sensor, logic-on-logic breakdowns
- Hybrid bonding disruption of TSV market share
Ch. 6
Regional Analysis
- Korea HBM and Japan image sensor TSV concentration
- North America Intel and Europe imec
Ch. 7
Competitive Analysis
- 15 company profiles and TSV platform comparison
- Equipment supplier TSV etch and fill competition
Ch. 8
Primary Research
- Interview panel - 18 process engineers and packaging leads
- Methodology and data validation